# *****************************************************************************
# resets
# *****************************************************************************
fpga_wr=W:0x00000F0:0x0001; # set ADC0 reload (adc0_reload)
usleep(.1)
fpga_wr=W:0x00000F0:0x0000; # clear ADC0 reload
usleep(.1)
fpga_wr=W:0x0000008:0x0004; # set ADC differential DDR reset (ctrl_reset)
usleep(.1)
fpga_wr=W:0x0000008:0x0000; # clear ADC differential DDR reset
usleep(.1)
fpga_wr=W:0x0000008:0x0020; # set ADC PLL reset (pll_rst)
usleep(.1)
fpga_wr=W:0x0000008:0x0000; # clear ADC PLL reset 
usleep(.1)
fpga_wr=W:0x0000008:0x0010; # set SYS PLL reset (sys_pll_rst)
usleep(.1)
fpga_wr=W:0x0000008:0x0000; # clear SYS PLL reset 
usleep(.1)
fpga_wr=W:0x0000008:0x2000; # set FPGA global reset (async_reset)
usleep(.1)
fpga_wr=W:0x0000008:0x0000; # clear FPGA global reset
usleep(.1)
fpga_wr=W:0x0000008:0x0001; # set internal PPS sync enable (ControlReg_i(0))
usleep(.1)
fpga_wr=W:0x0000008:0x0000; # clear internal PPS sync enable
usleep(.1)
# *****************************************************************************
# set attenuators
# *****************************************************************************
fpga_wr=W:0x00000E0:0x8181; # Set both attenuators to 16dB, solar off
usleep(.1)
# *****************************************************************************
# years from 2000
# *****************************************************************************
fpga_wr=W:0x800004:0x000C:  # set the number of years since 2000
usleep(.1)
# *****************************************************************************
# DC sub-band mode initialization
# *****************************************************************************
fpga_wr=W:0x200090:0x00FF;  # set all baseband mixers to mix up
usleep(.1)
# *****************************************************************************
# DC FTW initialization
# *****************************************************************************
fpga_wr=W:0x200050:0x0000;  # load lower half of weaver FTW
usleep(.1)
fpga_wr=W:0x200052:0x4000;  # load upper half of weaver FTW
usleep(.1)
# *****************************************************************************
# DC xbar initialization
# *****************************************************************************
fpga_wr=W:0x200040:0x0002;  # DC0 in sb2
usleep(.1)
fpga_wr=W:0x200042:0x0002;  # DC1 in sb2
usleep(.1)
fpga_wr=W:0x200044:0x0002;  # DC2 in sb2
usleep(.1)
fpga_wr=W:0x200046:0x0002;  # DC3 in sb2
usleep(.1)
fpga_wr=W:0x200048:0x0002;  # DC4 in sb2
usleep(.1)
fpga_wr=W:0x20004A:0x0002;  # DC5 in sb2
usleep(.1)
fpga_wr=W:0x20004C:0x0002;  # DC6 in sb2
usleep(.1)
fpga_wr=W:0x20004E:0x0002;  # DC7 in sb2
usleep(.1)
# *****************************************************************************
# set the m5b formatter data send times
# *****************************************************************************
#fpga_wr=W:0x0800014:0x0000; # Load lower half of Julian Date Start time
#usleep(.1)
#fpga_wr=W:0x0800016:0x0000; # Load upper half of Julian Date Start time
#usleep(.1)
#fpga_wr=W:0x0800018:0xFFFF; # Load lower half of Julian Date End time
#usleep(.1)
#fpga_wr=W:0x080001A:0xFFFF; # Load upper half of Julian Date End time
#usleep(.1)
# *****************************************************************************
# default quantizer thresholds
# *****************************************************************************
fpga_wr=W:0x600008:0x0E10; # load positive threshold
usleep(.1)
fpga_wr=W:0x60000A:0x0000; # load zero threshold
usleep(.1)
fpga_wr=W:0x60000C:0xF1F0; # load negative threshold
usleep(.1)
# *****************************************************************************
# tsys configuration
# *****************************************************************************
fpga_wr=W:0xE00000:0x8000; # CONTROL REGISTER, turn on control
usleep(.1)
fpga_wr=W:0xE00002:0X69FF; # DIODE FREQUENCY 256MHZ CLOCK CYCLES LSW
usleep(.1)
fpga_wr=W:0xE00004:0x0018; # DIODE FREQUENCY 256 MHZ CLOCK CYCLES MSW
usleep(.1)
fpga_wr=W:0xE00006:0x0200; # BLANKING PERIOD IN 256 MHZ CLOCK CYCLES 2USECS
usleep(.1)
fpga_wr=W:0xE00008:0x0000; # SCALING FACTOR 
usleep(.1)