Monitor and Control Hardware
Typical GBT receivers, those with four or fewer pixels, utilize a monitor and control system based on the VLBA Standard Interface Board. At the time the Standard Interface Board was designed it had more capacity than the foreseen needs of NRAO receivers, up to 256 digital control bits and 64 analog voltage inputs connected via an RS-485 Serial bus. The K-band Focal Plane Array with a projected 61 dual polarization pixels and associated down converters presents a need for on the order of a thousand digital control bits and two thousand analog voltage channels. Additionally, newer, complex GBT instruments are connected to the telescope network via Ethernet over optical fiber. Clearly a higher capacity Monitor and Control system is needed.
Distributed Monitor and Control
Since the K-band Focal Plane Array is a ‘distributed’ receiver with active modules spread over a large area relative to a traditional receiver the argument can be made for distributing the monitor and control system as well, especially since a central M + C system would require a formidable complex of wiring to achieve the necessary connections. For the K-band Focal Plane Array we plan to utilize the Inter-Integrated Circuit bus standard, or I2C
, for communicating commands and data between small Monitor and Control modules located in or near the distributed receiver components. This is a bi-directional, two wire, serial interface with one wire providing a clock running at up to 400 kHz and the other wire carrying commands and data to and from intelligent devices. Individual devices have three bit addresses and groups of eight will be isolated by gated bus buffers.
For biasing the cryogenic low noise amplifiers a constant drain current source is controlled by voltage references in turn adjusted by non-volatile, digital potentiometers. The non-volatility of the settings results in bias levels automatically returning to their previous settings immediately after power has been removed and restored. Not that resetting all the bias settings would be time consuming, to reset and verify the bias for all 488 amplifier stages takes less than a second. Verification of bias settings is done on the bias card by a pair of multi channel A/D converters that return the data to the controller over the I2C
Other components of the receiver would contain the necessary I2C
components for monitoring and control of their particular function and be addressed via the I2C
bus. More than one I2C
bus would be used with major groups of receiver components on a bus specific to their function.
- An Ethernet card with associated circuitry to monitor the receiver.
- Master controller would have one Ethernet connection to the outside world.
- Master controller would live in an RFI-tight box, with only power, fiber, and I2C lines exiting the enclosure.
- Pixel-select line 0 could be used for selection of global monitor and control points.
- IIC A/D converters and parallel I/O should be used to interface the global monitor points. Signal conditioning will be provided to put the signals in the best place to use the available bits of the A/D converter.
- Adjusting and monitoring of the bias would take place between scans or other times active observing is not taking place and the IIc bus will be dormant during observing to eliminate any possible RFI generated by the IIC bus.
Monitor and Control Points
- KFPA7MCB.xls: MCB IIc addressing data for the seven pixel receiver.
The usual M+C points of a GBT Receiver:
- LNA Bias Vdd and Idd.
- 15K, 50K and 300K stage temperatures.
- Power supply voltages.
- Dewar and Pump vacuum levels.
- Cryogenic system logic state (Control and Monitor).
- Calibration system logic state (Control and Monitor).
- CAL ON state
- LO1 levels
- Additional 15k and 50K monitors
- Calibration system monitoring: Vd(overall), Vg(overall), Id per pixel, ~63 points. The Id/pixel could be done with the planned LNA bias system by not monitoring Vg on the last LNA stages, monitoring Id-noise and V-LED, but there would need to be a command to fire the noise source and check the current between scans.
- Integrated Downconverter Modules: Power supplies V and I, LO Power and amp current levels, attenuator control bits per pixel, ~440 analog monitor points, ~610 digital control and monitor bits. Quite substantial, certainly something for the IIc bus concept, maybe it calls for an IIc M+C sub-card with 8-16 analog inputs and 16 digital in/outputs, in this case piggybacked on the down converter body or M+C/power connector.
- What else?
Current Bias Plan:
- A diagram of the system internal to the dewar is attached below.
- Use the IIc bus protocol to address bias adjustments and bias monitoring through the dewar wall, keeping the micro or single board outside the dewar and running the IIc bus through a hermetic connector.
- Inside the dewar will be a backplane carrying the cryogenic LNA bias regulator cards. IIc bus buffers controlled by a 16 channel I2C I/O expander control IIc communications with the bias cards, allowing only one card at a time to be addressed. The I/O expander has 3 user-configurable bits, 8 can be placed on the same I2C bus in future, expanded arrays.
- LNA On/Off by polarization will be controlled by 16 channel I2C I/O expanders. Each I/O expander has 3 user-configurable bits, 8 can be placed on the same I2C bus.
- Each pixel bias card supplies both polarizations and will have an IIc bus buffer/enable to address the particular pixel, a bias circuit covering all eight LNA stages and IIc, 12 channel A/D converters for monitoring of individual V-drain, I-drain V-gate and V-LED values. The A/D converters are available in 4 different base addresses per model number.
- Bias circuit will use the analog, LNA part of the ALMA bias circuit but will derive control voltages from voltage reference sources and non-volatile, IIc interface, digital potentiometers. Each non-vol pot has 3 user-configurable bits, 8 can be placed on the same I2C bus.
- Adjusting and monitoring would have to take place between scans or other times active observing is not taking place and the IIc bus shut off during observing.
Thermal Contribution of the Bias Wires
- Using figures from VLBA Technical Report 3, #32 brass (260) wires, 10 per LNA, 61 elements, 2 polarizations (1220 wires) from 300K to 15K loads the 15K stage with approximately 2.7 watts.
- Using figures from Lake Shore tables and from eq. 1 of NRAO EDIR 306, manganin wire 40 cm long, 10 per LNA, 61 elements, 2 polarizations (1220 wires) from 300K to 15K would put approximately 430 milliwatts into the 15K stage.
- Phosphor-bronze wire in the same conditions would put approximately 921 milliwatts into the 15K stage.
- #36 manganin wire in the same conditions would put approximately 168 milliwatts into the 15K stage.
- #36 Phosphor-bronze wire in the same conditions would put approximately 360 milliwatts into the 15K stage.
- Considering both conduction and dissipation due to lead resistance #32 manganin wire will have the lowest thermal contribution.
Notes on the Bias Design
Each amplifier requires 10 bias wires, so N (number of elements) x 2 = somewhere near 1200 wires.
How are all these bias wires managed?
- Locate the cards in the dewar and use a multiplex for the monitor points.
- Will the bias settings need to be changed after the dewar is pumped down and cooled? We're assuming 'yes,' and designing the system to do that.
- Is there room inside the dewar?
- Footprint of bias system must be no larger than the feed array footprint. Bias cards can be located anywhere within ~40cm of wire run from the LNA's.
Component Data Sheets:
: LK204-25 LCD IIc Display
: MAX5477-MAX5479 Series of Non-Volatile, Dual, Digital Potentiometers
: MAX1136-MAX1139M Series of 10 Bit, 12 Channel A/D Converters
: MAX1036-MAX1039M Series of 8 Bit, 12 Channel A/D Converters
: MAX320-MAX322 Analog Switches (MAX321)
: PCA9534 8 bit I/O expander
: PCA9535 16 Bit I/O Expander
: IES5501 IIc Bi-Directional Bus Buffer