VEGAS Pulsar BOF File Status

This page describes the status of the VEGAS Pulsar Mode bof files.

The naming convention for the mode names (and bof files) is encoded with this information:

MODE TYPE BANDWIDTH x # OF CHANNELS
where:
  • MODE TYPE will either be "i", "c", or "f" to represent "incoherent", "coherent", or "fast search", respectively
  • BANDWIDTH will either be 0100, 0200, 0800, or 1500 which represents the bandwidth in MHz
    • Note-- leading zeros are used for this to maintain consistent bof file name character lengths.
  • x is simply the character "x" as a delimiter between BW and # of channels
  • # OF CHANNELS will either be 0032, 0064, 0128, 0256, 0512, 1024, 2048, or 8192.
    • Note -- leading zeros are also used here for the same reason as above.

Example, the incoherent, 512 channel mode with 1500MHz BW will carry the name: i1500x0512

Example, the coherent, 128 channel mode with 200MHz BW will carry the name: c0200x0128

Also, note that all letters in the names must be lower case due to a restriction by the build tool filename.

Testing status is pass/fail:
  • Initial simulator tests (loading bof file and writing psrfits data in simulator)
  • Final simulator tests (taking multiple short and single long scans in simulator with timing analysis)
  • Initial GBT tests (taking basic scans of noise diode or pulsar)
  • Final GBT tests (taking scans of an MSP w/ flux calibration and basic timing analysis)

Original DIBAS Incoherent mode bof files

Mode Filename Date built Comments
i1500x0064 dibas_inco_0064_t12_w095_p00_2013_Aug_06_1328.bof 08/06/13 Xilinx version 14.3, Matlab R2012a
i1500x0128 dibas_inco_0128_t12_w095_p00_2013_Aug_06_1703.bof 08/06/13 Xilinx version 14.3, Matlab R2012a
i1500x0256 dibas_inco_0256_t12_w095_p00_2013_Aug_06_2036.bof 08/06/13 Xilinx version 14.3, Matlab R2012a
i1500x0512 dibas_inco_0512_t12_w095_p00_2013_Aug_06_2153.bof 08/06/13 Xilinx version 14.3, Matlab R2012a
i1500x1024 dibas_inco_1024_t12_w095_p00_2013_Aug_07_1354.bof 08/07/13 Xilinx version 14.3, Matlab R2012a
i0500x1024 dibas_inco_1024_t12_w095_p01_2013_Oct_10_1437.bof 10/10/13 Xilinx version 14.3, Matlab R2012a
i1500x2048 dibas_inco_2048_t12_w095_p00_2013_Aug_05_1926.bof 08/05/13 Xilinx version 14.3, Matlab R2012a
i1500x4096 dibas_inco_4096_t12_w095_p00_2013_Aug_19_1310.bof 08/19/13 Xilinx version 14.3, Matlab R2012a
i1500x8192 dibas_inco_8192_t12_w095_p00_2013_Aug_14_1143.bof 08/14/13 Xilinx version 14.3, Matlab R2012a

Original DIBAS fast search mode bof files

Mode Filename Date built Comments
f1500x4096 dibas_fast_4096_t12_w095_p00_2013_Aug_08_1053.bof 08/08/13 Xilinx version 14.3, Matlab R2012a

Original DIBAS Coherent mode bof files

Mode Filename Date built Comments
c1500x0064 dibas_codd_0064_t12_w095_p00_2013_Oct_04_1039.bof 10/04/13 Xilinx version 14.3, Matlab R2012a
c1500x0128 dibas_codd_0128_t12_w095_p00_2013_Oct_04_1406.bof 10/04/13 Xilinx version 14.3, Matlab R2012a
c1500x0256 dibas_codd_0256_t12_w095_p00_2013_Oct_07_1319.bof 10/07/13 Xilinx version 14.3, Matlab R2012a
c0500x0256 dibas_codd_0256_t12_w095_p01_2013_Oct_10_1047.bof 10/10/13 Xilinx version 14.3, Matlab R2012a
c1500x0512 dibas_codd_0512_t12_w095_p00_2013_Oct_07_1325.bof 10/07/13 Xilinx version 14.3, Matlab R2012a
c1500x1024 dibas_codd_1024_t12_w095_p00_2013_Oct_04_2241.bof 10/04/13 Xilinx version 14.3, Matlab R2012a
c1500x2048 dibas_codd_2048_t12_w095_p00_2013_Oct_04_1902.bof 10/04/13 Xilinx version 14.3, Matlab R2012a
c1500x4096 dibas_codd_4096_t12_w095_p00_2013_Oct_03_2152.bof 10/03/13 Xilinx version 14.3, Matlab R2012a
c1500x8192 dibas_codd_8192_t12_w095_p00_2013_Oct_03_2217.bof 10/03/13 Xilinx version 14.3, Matlab R2012a

Production VEGAS Incoherent mode bof files

These tables contain a new column labeled "Parent/Child". This is intended to assist in the build process.

The "Parent" designs will require development time to sort out all the issues so that they work properly.

The "Child" designs only require a few minor edits to the associated "Parent" design, and a subsequent rebuild, meaning no development is required to generate these bof files, assuming they build successfully and meet timing of course.

The "Priority" columns below are based on the VEGAS Pulsar Mode Table here: VEGAS Pulsar Mode Table

Mode Filename Date built Parent/Child Priority Testing Status Comments
i0800x2048 i0800x2048_x14_7_2016_Apr_19_1048.bof 04/19/16 "Parent B" HIGH Passed Randy & Jason's manual testing Xilinx version 14.7, Matlab R2012b
  i0800x2048_x14_7_ss_2015_Dec_16_1028.bof 12/16/15 "Parent B" HIGH Passed initial sim tests Xilinx version 14.7, Matlab R2012b
i0200x2048 filename.bof mm/dd/yy "Parent C" HIGH - Xilinx version ??, Matlab R??
i1500x0032 filename.bof mm/dd/yy "Parent F" MEDIUM - Xilinx version ??, Matlab R??
i0800x0032 filename.bof mm/dd/yy "Child F" MEDIUM - Xilinx version ??, Matlab R??
i0800x0064 i0800x0064_x14_7_2016_Apr_19_1256.bof 04/19/16 "Child B" MEDIUM Passed Randy & Jason's manual testing Xilinx version 14.7, Matlab R2012b
  i0800x0064_x14_7_2015_May_30_1719.bof 05/30/15 "Child B" MEDIUM Failed initial sim tests (unexpected bandpass) Xilinx version 14.7, Matlab R2012b
i1500x0064 i1500x0064_x14_7_2016_Apr_19_0813.bof 04/19/16 "Child B" HIGH Passed Randy & Jason's manual testing Xilinx version 14.7, Matlab R2012b
  i1500x0064_x14_7_2015_Jun_01_1918.bof 06/01/15 "Child B" HIGH Failed initial sim tests (unexpected bandpass) Xilinx version 14.7, Matlab R2012b
i0800x0128 i0800x0128_x14_7_2016_Apr_19_1249.bof 04/19/16 "Child B" MEDIUM Passed Randy & Jason's manual testing Xilinx version 14.7, Matlab R2012b
  i0800x0128_x14_7_2015_May_31_0717.bof 05/31/15 "Child B" MEDIUM Failed initial sim tests (unexpected bandpass) Xilinx version 14.7, Matlab R2012b
i1500x0128 i1500x0128_x14_7_2016_Apr_20_1411.bof 04/20/16 "Child B" MEDIUM Passed Randy & Jason's manual testing Xilinx version 14.7, Matlab R2012b
  i1500x0128_x14_7_2015_Jul_17_1605.bof 07/17/15 "Child B" MEDIUM Failed initial sim tests (unexpected bandpass) Xilinx version 14.7, Matlab R2012b
i0800x0256 i0800x0256_x14_7_2016_Apr_19_1242.bof 04/19/16 "Child B" MEDIUM Passed Randy & Jason's manual testing Xilinx version 14.7, Matlab R2012b
  i0800x0256_x14_7_2015_Jun_04_2301.bof 06/04/15 "Child B" MEDIUM Passed initial sim tests Xilinx version 14.7, Matlab R2012b
i1500x0256 i1500x0256_x14_7_2016_Apr_19_0753.bof 04/19/16 "Child B" MEDIUM Passed Randy & Jason's manual testing Xilinx version 14.7, Matlab R2012b
  i1500x0256_x14_7_2015_Jul_17_0922.bof 07/17/15 "Child B" MEDIUM Failed initial sim tests (unexpected bandpass) Xilinx version 14.7, Matlab R2012b
i0800x0512 i0800x0512_x14_7_2016_Apr_19_1104.bof 04/19/16 "Child B" MEDIUM Passed Randy & Jason's manual testing Xilinx version 14.7, Matlab R2012b
  i0800x0512_x14_7_2015_May_17_2357.bof 05/17/15 "Child B" MEDIUM Passed initial sim tests Xilinx version 14.7, Matlab R2012b
i1500x0512 i1500x0512_x14_7_2016_Apr_18_1253.bof 04/18/16 "Child B" HIGH Passed Randy & Jason's manual testing Xilinx version 14.7, Matlab R2012b
  i1500x0512_x14_7_2015_Jul_01_1649.bof 07/01/15 "Child B" HIGH Passed initial sim tests Xilinx version 14.7, Matlab R2012b
i0100x1024 filename.bof mm/dd/yy "Child C" MEDIUM - Xilinx version ??, Matlab R??
i0200x1024 filename.bof mm/dd/yy "Child C" MEDIUM - Xilinx version ??, Matlab R??
i0800x1024 i0800x1024_x14_7_2016_Apr_19_1054.bof 04/19/16 "Child B" MEDIUM Passed Randy & Jason's manual testing Xilinx version 14.7, Matlab R2012b
  i0800x1024_x14_7_2015_May_13_2000.bof 05/13/15 "Child B" MEDIUM Passed initial sim tests Xilinx version 14.7, Matlab R2012b
i1500x1024 i1500x1024_x14_7_2016_Apr_18_1521.bof 04/18/16 "Child B" HIGH Passed Randy & Jason's manual testing Xilinx version 14.7, Matlab R2012b
  i1500x1024_x14_7_2015_Jun_26_1625.bof 06/26/15 "Child B" HIGH Passed initial sim tests Xilinx version 14.7, Matlab R2012b
i0100x2048 filename.bof mm/dd/yy "Child C" MEDIUM - Xilinx version ??, Matlab R??
i1500x2048 i1500x2048_x14_7_2016_Apr_18_1509.bof 04/18/16 "Child B" HIGH Passed Randy & Jason's manual testing Xilinx version 14.7, Matlab R2012b
  i1500x2048_x14_7_ss_2015_Dec_15_1510.bof 12/15/15 "Child B" HIGH Passed initial sim tests Xilinx version 14.7, Matlab R2012b
i0100x4096 filename.bof mm/dd/yy "Child C" MEDIUM - Xilinx version ??, Matlab R??
i0200x4096 filename.bof mm/dd/yy "Child C" MEDIUM - Xilinx version ??, Matlab R??
i0800x4096 i0800x4096_x14_7_2016_Apr_19_1038.bof 04/19/16 "Child B" MEDIUM Passed Randy & Jason's manual testing Xilinx version 14.7, Matlab R2012b
  i0800x4096_x14_7_2015_May_22_2349.bof 05/22/15 "Child B" MEDIUM Passed initial sim tests Xilinx version 14.7, Matlab R2012b
i1500x4096 i1500x4096_x14_7_2016_Apr_18_0932.bof 04/18/16 "Child B" MEDIUM Passed Randy & Jason's manual testing Xilinx version 14.7, Matlab R2012b
  i1500x4096_x14_7_2015_Jun_26_0835.bof 06/26/15 "Child B" MEDIUM Passed initial sim tests Xilinx version 14.7, Matlab R2012b
i0100x8192 filename.bof mm/dd/yy "Child C" MEDIUM - Xilinx version ??, Matlab R??
i0200x8192 filename.bof mm/dd/yy "Child C" MEDIUM - Xilinx version ??, Matlab R??
i0800x8192 i0800x8192_x14_7_2016_Apr_19_0843.bof 04/19/16 "Child B" MEDIUM Passed Randy & Jason's manual testing Xilinx version 14.7, Matlab R2012b
  i0800x8192_x14_7_2015_May_30_1752.bof 05/30/15 "Child B" MEDIUM Failed initial sim tests (repeated signal) Xilinx version 14.7, Matlab R2012b
i1500x8192 i1500x8192_x14_7_2016_Apr_18_0901.bof 04/18/16 "Child B" MEDIUM Passed Randy & Jason's manual testing Xilinx version 14.7, Matlab R2012b
  i1500x8192_x14_7_2015_Jul_21_1543.bof 07/21/15 "Child B" MEDIUM Failed initial sim tests (unexpected bandpass) Xilinx version 14.7, Matlab R2012b

Production VEGAS fast search mode bof files

Mode Filename Date built Parent/Child Priority Testing Status Comments
f0100x4096 filename.bof mm/dd/yy "Parent E" HIGH - Xilinx version ??, Matlab R??
f1500x4096 f1500x4096_x14_7_2015_Jul_15_1553.bof 07/15/15 "Parent H" MEDIUM - Xilinx version 14.7, Matlab R2012b
f0200x4096 filename.bof mm/dd/yy "Child E" MEDIUM - Xilinx version ??, Matlab R??
f0800x4096 f0800x4096_x14_7_2015_May_15_1821.bof 05/15/15 "Child H" MEDIUM - Xilinx version 14.7, Matlab R2012b
f0100x8192 filename.bof mm/dd/yy "Child E" SPECIAL CASE - Xilinx version ??, Matlab R??
f0200x8192 filename.bof mm/dd/yy "Child E" MEDIUM - Xilinx version ??, Matlab R??
f0800x8192 f0800x8192_x14_7_2015_Jun_06_1759.bof 06/06/15 "Child H" MEDIUM - Xilinx version 14.7, Matlab R2012b
f1500x8192 f1500x8192_x14_7_2015_Jul_24_0826.bof 07/24/15 "Child H" MEDIUM - Xilinx version 14.7, Matlab R2012b

Production VEGAS Coherent mode bof files

Mode Filename Date built Parent/Child Priority Testing Status Comments
c0800x0512 c0800x0512_x14_7_2016_Feb_29_1611.bof 02/29/16 "Parent A" HIGH Passed initial sim tests Xilinx version 14.7, Matlab R2012b
c0200x0128 filename.bof mm/dd/yy "Parent D" HIGH - Xilinx version ??, Matlab R??
c1500x0032 filename.bof mm/dd/yy "Parent G" SPECIAL CASE - Xilinx version ??, Matlab R??
c0100x0032 filename.bof mm/dd/yy "Child D" MEDIUM - Xilinx version ??, Matlab R??
c0200x0032 filename.bof mm/dd/yy "Child D" MEDIUM - Xilinx version ??, Matlab R??
c0800x0032 filename.bof mm/dd/yy "Child G" MEDIUM - Xilinx version ??, Matlab R??
c0100x0064 filename.bof mm/dd/yy "Child D" MEDIUM - Xilinx version ??, Matlab R??
c0200x0064 filename.bof mm/dd/yy "Child D" MEDIUM - Xilinx version ??, Matlab R??
c0800x0064 c0800x0064_x14_7_2016_Mar_11_0859.bof 03/11/16 "Child A" MEDIUM Passed Randy & Jason's manual testing Xilinx version 14.7, Matlab R2012b
  c0800x0064_x14_7_2015_May_21_2313.bof 05/21/15 "Child A" MEDIUM Failed initial sim tests (scan failed to start) Xilinx version 14.7, Matlab R2012b
c1500x0064 filename.bof mm/dd/yy "Child A" SPECIAL CASE - Xilinx version ??, Matlab R??
c0100x0128 filename.bof mm/dd/yy "Child D" MEDIUM - Xilinx version ??, Matlab R??
c0800x0128 c0800x0128_x14_7_2016_Mar_10_1144.bof 03/10/16 "Child A" MEDIUM Passed Randy & Jason's manual testing Xilinx version 14.7, Matlab R2012b
  c0800x0128_x14_7_2015_May_22_0241.bof 05/22/15 "Child A" MEDIUM Failed initial sim tests (packet sequence errors) Xilinx version 14.7, Matlab R2012b
c1500x0128 c1500x0128_x14_7_2016_Mar_05_1423.bof 03/05/16 "Child A" SPECIAL CASE Passed initial sim tests Xilinx version 14.7, Matlab R2012b
c0100x0256 filename.bof mm/dd/yy "Child D" MEDIUM - Xilinx version ??, Matlab R??
c0200x0256 filename.bof mm/dd/yy "Child D" MEDIUM - Xilinx version ??, Matlab R??
c0800x0256 c0800x0256_x14_7_2016_Mar_10_1136.bof 03/10/16 "Child A" MEDIUM Passed Randy & Jason's manual testing Xilinx version 14.7, Matlab R2012b
  c0800x0256_x14_7_2015_Jun_05_1912.bof 06/05/15 "Child A" MEDIUM Passed initial sim tests Xilinx version 14.7, Matlab R2012b
c1500x0256 c1500x0256_x14_7_2016_Mar_04_1344.bof 03/04/16 "Child A" SPECIAL CASE Passed initial sim tests Xilinx version 14.7, Matlab R2012b
c0100x0512 filename.bof mm/dd/yy "Child D" MEDIUM - Xilinx version ??, Matlab R??
c0200x0512 filename.bof mm/dd/yy "Child D" MEDIUM - Xilinx version ??, Matlab R??
c1500x0512 c1500x0512_x14_7_2016_Feb_24_1437.bof 02/24/16 "Child A" SPECIAL CASE Passed initial sim tests Xilinx version 14.7, Matlab R2012b
c0800x1024 c0800x1024_x14_7_2016_Mar_09_1450.bof 03/09/16 "Child A" SPECIAL CASE Passed Randy & Jason's manual testing Xilinx version 14.7, Matlab R2012b
c1500x1024 c1500x1024_x14_7_2016_Mar_03_1319.bof 03/03/16 "Child A" SPECIAL CASE Passed initial sim tests (dropped packets as expected) Xilinx version 14.7, Matlab R2012b
c0800x2048 c0800x2048_x14_7_2016_Mar_09_1445.bof 03/09/16 "Child D" SPECIAL CASE Passed Randy & Jason's manual testing Xilinx version 14.7, Matlab R2012b
c1500x2048 c1500x2048_x14_7_2016_Mar_02_1218.bof 03/02/16 "Child A" SPECIAL CASE Failed initial sim tests (bandpass appears saturated in low channels regardless of scale) Xilinx version 14.7, Matlab R2012b
c0800x4096 c0800x4096_x14_7_2016_Mar_09_1415.bof 03/09/16 "Child A" SPECIAL CASE Passed Randy & Jason's manual testing Xilinx version 14.7, Matlab R2012b
  c0800x4096_x14_7_ss_2015_Dec_17_0953.bof 12/17/16 "Child A" SPECIAL CASE Failed initial sim tests (packets not flowing) Xilinx version 14.7, Matlab R2012b
c1500x4096 c1500x4096_x14_7_2016_Feb_19_1357.bof 02/19/16 "Child A" SPECIAL CASE Passed initial sim tests (dropped packets as exepected) Xilinx version 14.7, Matlab R2012b

Documentation

The user documentation for the latest VEGAS INCO mode firmware can be found here: VPM INCO-mode user documentation

The user documentation for the latest VEGAS CoDD mode firmware can be found here: VPM CoDD-mode user documentation

-- RichardPrestage - 2015-02-26
Topic attachments
I Attachment Action Size Date Who Comment
VPM_CODD_DOC.pdfpdf VPM_CODD_DOC.pdf manage 103.5 K 2015-07-23 - 10:21 ArindamSengupta VPM CoDD-mode user documentation
VPM_INCO_DOC.pdfpdf VPM_INCO_DOC.pdf manage 104.0 K 2015-07-23 - 10:20 ArindamSengupta VPM INCO-mode user documentation
c0800x0128_x14_7.slxslx c0800x0128_x14_7.slx manage 1053.4 K 2017-06-26 - 16:00 JasonRay  
codd_fft_0128ch_core.slxslx codd_fft_0128ch_core.slx manage 3435.4 K 2017-06-26 - 16:01 JasonRay  
codd_pfb_fir_0128ch_core.slxslx codd_pfb_fir_0128ch_core.slx manage 1052.9 K 2017-06-26 - 16:00 JasonRay  
Topic revision: r57 - 2017-06-26, JasonRay
 

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