VEGAS Bank Discrepancy Problem - 21 January 2015

More attempts to diagnose the cause of this problem, after the requantization balancing fix.

Experimental setup

Jason connected the noise source to an eight-way splitter, to Banks E,F,G,H, both polarizations. Even with no noise source attenuation, the input power level was slightly low, so Jason replaced the pads on the inputs to the ADCs with 3dB pads. This brought the input power level (as measured by the VEGAS measpwr samplers) to around -20 - -21dB.

Data was taken into TGBT14A_912_62. Here is the observing log

The archivist was set to log all of the available measpwr samplers. VEGAS was initially configured using the config_tool. This set lbw_gain levels to try to match the FPGA output sampler values (i.e. flitersnap, or snNsnap, respectively) to match the input measpwr values. For modes 11,21 and 22, the lbw_gain values had to be set to 16384 rather than the more usual 1024. Might this be related to the nosie source bandpass shape?

With the noise source output attenuation set to 0dB, a 60 second tp_nocal measurement was made, and samplers and spectra recorded to disk. The process was then repeated with the noise source output attenuation set to 1dB, 2dB and 5dB.

Preliminary results.

So, far, I have only looked at ADC samplers (not spectra). For both the input sampler (measpwr) and the post-balancing sampler (either filtersnap or sb1snap), the second scan was divided by the first scan. The expected ratios for both input and output are then -1dB, or 0.7943 in linear units. The actual results obtained are show in the plots below. In these plots, the value is the mean of the ~ 60 samples obtained within the 60 second scan (averaged in linear units), and the error bars are the standard deviation of these values.
  • Mode 4:
    Mode4.png

  • Mode 7:
    Mode7.png

  • Mode 11:
    Mode11.png

  • Mode 21:
    Mode21.png

  • Mode 22:
    Mode22.png

Similar results were obtained for the 2dB and 5dB attenuations, with the typical results being:

nominal atten   measured atten
      1dB                   0.7dB
      2dB                   1.5 dB
      5dB                    3.5dB

Conclusions

  • The problem is not in the analog electronics or the ADC (since the input power measurements are as expected). For all modes, the ratio of the input measpwr samplers agrees within the errors to the expected value of -1 dB (0.7943).
  • The problem is in the FPGA.
    • For modes 4, 11, 21 and 22, the ratios are systematically high, ranging from -1dB to only -0.45dB (0.78 to 0.9 in linear units).
    • Mode 11, which seemed a "good" mode from the earlier Tsys investigations, is the worst mode here.
    • Mode 7, which gave mixed results from the earlier Tsys investigations now seems anomalously good.
Topic attachments
I Attachment Action Size Date Who Comment
Mode11.pngpng Mode11.png manage 33 K 2015-01-21 - 19:08 RichardPrestage Mode 11
Mode21.pngpng Mode21.png manage 33 K 2015-01-21 - 19:08 RichardPrestage Mode 21
Mode22.pngpng Mode22.png manage 33 K 2015-01-21 - 19:08 RichardPrestage Mode 22
Mode4.pngpng Mode4.png manage 33 K 2015-01-21 - 19:07 RichardPrestage Mode 4
Mode7.pngpng Mode7.png manage 32 K 2015-01-21 - 19:07 RichardPrestage Mode 7
Topic revision: r2 - 2015-03-07, RichardPrestage
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