Chart of dates for initial functions for integration and first test planning

Group	Function	Available	Comments
Analog IF System
	IF input	mid Sept	Prototype
	CLK input from synth/splitter	Now
	1 PPS	Now	May not need clock splitter for initial tests
digital status bits	signal switching system	Mid Sept	PCBs and parts are now all on order with promised delivery dates of 15-AUG-2011 or sooner
	noise on/off, beam on/off	mid Sept
roach 10Gbe	output to back end computer to filler to disk	Now	we could test through a switch
100Mbe	Roach control connection		fan speeds, voltages (not supported by Roach2)
Modes to test
	mode 1 (1 band)		Output: FITS file (follows shared memory dev.)
	8 sub-bands of 15 MHz
	shared memory interface		one of the more difficult interface - minor dependency on Bob's work
Manager (M&C)
	1Gbe monitor and control	Aug 16 (If 1st priority)	can we set up the roach and the GPU/CPU, monitor the ADC levels
Data Reduction Pipeline	file-based and off-line using sdfits as input (phase0)	Oct	all of the changes are upstream of the pipeline to allow it to work as it does now
Simulator	creates the shared memory, sends some dummy data etc for M&C interfacing	(15-Jul)	At UC-B
	HPC and roach simulator	Now	At NRAO
Roach1 Boards

• Aug 8 - 14
• Aug 16 - 21
• Nov 24 - 27 (Thanksgiving weekend)
• Dec 17 onwards (end of final examinations)