We are still trying to track down the source of the non Fs/64 spikes. Run integrations with a digital noise source in the FPGA, instead of the ADC. This will confirm or rule out that it is after the ADC.
Recheck the RRL C-band configuration
FPGA Noise source Tests
Start at 8:00am
Ray loads the l8_ver170_1500_x02_2015_Jun_12_1922.bof boffile
Goal is to set eight sub-bands (just one bank) to certain locations in the ADC passband. Since comparison tests will be done with the hardware noise source (if at all), the actual IF information, etc, is irrelevant.
So, set up for C-band (5GHz), and space band centers symmetrically around this.
per John, offset banks by 27MHz, and put two on 5.0GHz. So, we want mode 24, with:
4919, 4946, 4973, 5000, 5000, 5027, 5054, 5081
configure for tp_nocal scans, initially 1sec switch period and integration
ignore MMCM messages (no ADC...
Steve is working on LO1 - remove it from scan coordinator?
Doesn't help. But VEGAS has been configured (I think), so proceed.
VEGAS dBFS is 0.1dB, and bank is totally saturating in "ADC" (whatever this means). Running balance() doesn't help...
lbw_gain is initially 21. Setting it to e.g. 3 makes sb1snap look good, but input samplers are still saturated. Check with Jason...
He says there is a bug in the FPGA code which was not caught before, and this version will not work. Abandon the test.
RRL C-band configuration
Start at 1:30pm. Bob Simon is still working on LO1
Run RRL_w3_crrl_nopk - same problem as last week.
The LO in Converter Rack CM1 is set to 14625, which seems too high (IF in is 2464).
We see that the problem (or at least partially) is in the Rx output. The IF from the first mix is 1-5 GHz, but that is followed by a (claimed) 0-4GHz filter
Steve recommends for wideband, we should put the LO at 11 GHz, and then the If output will be 7 - 3 GHz