Testing lbw_gain and balancing

Goals

Vary input levels, vary lbw_gain and monitor measpwr and the appropriate scaled output values

Details

Steve has the system, so we have to work manually,using only VEGAS and the converter rack CLEO screens,

Bank D seems to have power going in to it, so use that - ADC J7 adcpwr1. Mode 9 -20dBm

     lbw_gain      measpwr      filtersnap
2**25      33554432    -20             -42
2**26      67108864    -20             -39
2**27     134217728   -20              -34
2**28     268435456  -20              -28
2**29.5  759250124   -20              -19.5
2**30   1073741824   -20              -16.5
2**30.5 1518500249  -20              -13.5
2**31    2147483648  -20              -10.0
2**30.5 1518500249  -20              -13.5
2**30     1073741824 -20              -16.5
2**29.5   759250124  -20              -19.5
2**29      536870912  -20              -22.5
2**28.5   379625062  -20              -25.5
2**28      268435456  -20              -28.5
2**27.5   189812531  -20              -31.5
2**27      134217728  -20              -32.0
2**26.5   94906265    -20              -37.0
2**26      67108864    -20              -39.0
2**25.5   47453132    -20              -42.0
2**25      33554432   -20               -44.0

Mode 9, - 17dBm

2**25     33554432   -17    -42
2**25.5  47453132   -17    -39
2**26     67108864   -17    -36
2**26.5  94906265   -17    -33
2**27     134217728  -17   -30
2**27.5  189812531 -17    -27.5

lose IF input power to VEGAS at this point... then comes back again 2**27.5 189812531 -17 -46.5, and all values are 0 / 255. It is like the FPGA program is not updating these values.

I cannot find anyone to trouble-shoot this problem, so just give up at this point.

-- RichardPrestage - 2014-12-23
Topic revision: r3 - 2015-01-27, RichardPrestage
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