List of GUPPI BOF Files

This page has a list of all .bof files present on beef and any notable features about them

General notes

The bof file naming convention has evolved over time. Current practice is to label each design with a 3-character code (eg "P01", "T33" etc) as a form of versioning. "P" designs are meant to be production versions. "T" designs are test/development versions which may evolve into "P" versions at some point. "D", "X", "Y" and "Z" have all been used to denote debug versions, these often have various features removed/disabled for test purposes and generally should be avoided.

Other typical info in the file names includes the FPGA the design is meant for ("U1", "U2" etc), its basic purpose ("DSP", "OUT" etc), number of channels, and the date/time it was built.

XAUI alignment design (FPGA4)

bGXAL_U4_XXXX_1SFA_P00_fpga4_2009_Jun_15_1455.bof
This one design should be used with all current GUPPI1 and GUPPI2 bof sets.

Output designs (FPGA2)

GUPPI1 1SFA designs

bGOUT_U2_0064_1SFA_P00_fpga2_2010_Jan_14_1153.bof
bGOUT_U2_0128_1SFA_P00_fpga2_2009_May_14_1515.bof
bGOUT_U2_0256_1SFA_P00_fpga2_2009_Jul_07_0843.bof
bGOUT_U2_0512_1SFA_P00_fpga2_2009_Jul_06_1540.bof
bGOUT_U2_1024_1SFA_P00_fpga2_2009_Jul_06_1118.bof
bGOUT_U2_2048_1SFA_P00_fpga2_2009_Jun_04_1032.bof
bGOUT_U2_4096_1SFA_P00_fpga2_2009_Jul_08_0822.bof
bGOUT_U2_4096_1SFA_P00_fpga2_2009_Jul_14_0927.bof
bGOUT_U2_4096_1SFA_P01_fpga2_2009_Sep_03_1003.bof
These designs are used in incoherent filterbank (GUPPI1) modes. The 4096-channel P01 bof is a special "fast-dump" version that allows very short accumulations but only outputs total-intensity data.

CoDD designs

bGOUT_U2_1SFA_CoDD_P00_fpga2_2010_Jan_12_1332.bof
bGOUT_U2_1SFA_CoDD_P01_fpga2_2010_Jan_22_1617.bof
bGOUT_U2_1SFA_CoDD_P02_fpga2_2010_Feb_04_1245.bof
bGOUT_U2_1SFA_CoDD_P04_fpga2_2010_Feb_05_1212.bof
bGOUT_U2_1SFA_CoDD_P04_fpga2_2010_Feb_10_1036.bof
bGOUT_U2_1SFA_CoDD_P04_fpga2_2010_Feb_10_1509.bof
bGOUT_U2_1SFA_CoDD_P04_fpga2_2010_Feb_10_1556.bof
bGOUT_U2_1SFA_CoDD_P05_fpga2_2010_Feb_11_1123.bof
bGOUT_U2_1SFA_CoDD_P06_fpga2_2010_Feb_12_0931.bof
These are used to output baseband data for GUPPI2 coherent dedispersion modes. Starting with P01, the N_CHAN register should be set to log2(nchan). The various P04 versions have different ARP behavior enabled. Starting with P05, the 10Ge reset line is not used solving a random lockup problem. P05 uses the original ARP code. P06 is the same as P05 except with updated ARP code so that ARP packets are only sent on initialization rather than continuously.

DSP designs (FPGAs 1 and 3)

T012 designs

bGDSP_U1_0512_T012_P00_fpga1_2010_Feb_01_1531.bof
bGDSP_U1_0512_T012_P01_fpga1_2010_Feb_02_1048.bof
bGDSP_U3_0512_T012_P00_fpga3_2010_Feb_01_1555.bof
bGDSP_U3_0512_T012_P01_fpga3_2010_Feb_02_0857.bof
These have 12-tap PFBs. Version P00 has 1.0 width, and P01 has 0.95 width.

1248_P02 design

bGDSP_U1_0128_1248_P02_fpga1_2009_Dec_31_2011.bof
bGDSP_U3_0128_1248_P02_fpga3_2009_Dec_31_2011.bof
These are the same as the 128-channel P01 version except the PFBs are 8-tap, 1.0 width.

1248_P01 designs

bGDSP_U1_0064_1248_P00_fpga1_2010_Jan_14_0928.bof
bGDSP_U1_0128_1248_P01_fpga1_2009_Dec_31_1149.bof
bGDSP_U1_0256_1248_P01_fpga1_2009_Dec_31_1522.bof
bGDSP_U1_0512_1248_P01_fpga1_2009_Dec_31_1616.bof
bGDSP_U3_0128_1248_P01_fpga3_2009_Dec_31_1153.bof
bGDSP_U3_0256_1248_P01_fpga3_2009_Dec_31_1522.bof
bGDSP_U3_0512_1248_P01_fpga3_2009_Dec_31_1616.bof
bGDSP_U3_0064_1248_P00_fpga3_2010_Jan_14_0942.bof
These designs fix the PFB-FFT sync bug mentioned below. Note that the although the 64-channel version is labelled P00, it does have this fix. All PFBs are 4-tap, 1.0 width.

1248_P00 designs

bGDSP_U1_0128_1248_P00_fpga1_2009_Dec_17_1302.bof
bGDSP_U1_0128_1248_P00_fpga1_2009_May_11_1646.bof
bGDSP_U1_0128_1248_P00_fpga1_2009_May_29_1214.bof
bGDSP_U1_0256_1248_P00_fpga1_2009_Jul_07_1057.bof
bGDSP_U1_0512_1248_P00_fpga1_2009_Jul_07_0710.bof
bGDSP_U1_1024_1248_P00_fpga1_2009_Jul_06_1330.bof
bGDSP_U1_2048_1248_P00_fpga1_2009_Jun_03_1645.bof
bGDSP_U1_4096_1248_P00_fpga1_2009_Jul_06_0847.bof
bGDSP_U3_0128_1248_P00_fpga3_2009_Dec_17_1303.bof
bGDSP_U3_0128_1248_P00_fpga3_2009_May_11_1823.bof
bGDSP_U3_0128_1248_P00_fpga3_2009_May_29_1111.bof
bGDSP_U3_0256_1248_P00_fpga3_2009_Jul_07_1129.bof
bGDSP_U3_0512_1248_P00_fpga3_2009_Jul_07_0746.bof
bGDSP_U3_1024_1248_P00_fpga3_2009_Jul_06_1408.bof
bGDSP_U3_2048_1248_P00_fpga3_2009_Jun_03_1725.bof
bGDSP_U3_4096_1248_P00_fpga3_2009_Jul_06_0929.bof
These are the standard designs in use by the GUPPI1 filterbank modes. All PFBs are 4-taps, 1.0 width. These designs have a bug between the PFB-FFT blocks that causes large channel leakage in the 128 and 256 channel modes.

Deprecated designs

Everything past this point is not in current use, but is left here for reference purposes.

2048-channel designs

b2_GDSP_U1_4K_800_A_XA_fpga1_2008_Jul_30_1356.bof
b2_GDSP_U3_4K_800_A_XA_fpga3_2008_Jul_30_1414.bof
b2_GOUT_U2_4K_800_A_03_fpga2_2008_Aug_20_1555.bof
b2_GOUT_U2_4K_800_A_JR_fpga2_2008_Sep_05_1047.bof
b2_GOUT_U2_4K_800_A_LB_fpga2_2008_Sep_15_0950.bof
b2_GOUT_U2_4K_800_A_NR_fpga2_2008_Sep_15_1400.bof

Notes:
  • These are the "standard" 2048-channel designs in use for regular observations.
  • We typically use the Sep_15_1400 file in FPGA2. Are the older ones relevant anymore?

4096-channel "248" designs

bGDSP_U1_8K_248_A_00_fpga1_2008_Oct_22_1407.bof
bGDSP_U1_8K_248_A_XX_fpga1_2008_Nov_07_1349.bof
bGDSP_U3_8K_248_A_00_fpga3_2008_Oct_22_1427.bof
bGDSP_U3_8K_248_A_XX_fpga3_2008_Nov_07_1407.bof
bGOUT_U2_8K_248_A_00_fpga2_2008_Oct_23_1014.bof
bGOUT_U2_8K_248_A_01_fpga2_2008_Oct_28_1619.bof
bGOUT_U2_8K_248_A_03_fpga2_2008_Nov_05_1609.bof

Notes:
  • "248" designs are meant to work at 200, 400, or 800 MHz clock rates. In practice they don't work at 800 MHz but seem to be ok at lower BWs.
  • The GUPPi_PIPES_BW_SEL register on FPGA2 should be set to 1 for 400 MHz or 2 for 200 or 800 MHz.
  • What's the difference between the Oct/Nov versions? Are the older ones still needed?

4096-channel "400" and "800" designs

b2_GDSP_U1_8K_400_A_GB_fpga1_2008_Oct_21_1441.bof
b2_GDSP_U1_8K_400_A_PP_fpga1_2008_Oct_14_1039.bof
b2_GDSP_U3_8K_400_A_FB_fpga3_2008_Oct_10_1131.bof
b2_GDSP_U3_8K_400_A_GB_fpga3_2008_Oct_21_1502.bof
b2_GOUT_U2_8K_400_A_NR_fpga2_2008_Oct_22_1029.bof

b2_GDSP_U1_8K_800_A_FB_fpga1_2008_Aug_26_1143.bof
b2_GDSP_U1_8K_800_A_NB_fpga1_2008_Oct_09_1645.bof
b2_GDSP_U3_8K_800_A_NB_fpga3_2008_Oct_01_1037.bof
b2_GOUT_U2_8K_800_A_NR_fpga2_2008_Sep_30_1212.bof

Notes:
  • I don't know anything about these. Do they work?

4096-channel "1SFA" designs

bGOUT_1SFA_01_fpga2_2009_Jan_07_1129.bof
bGOUT_1SFA_DC2_fpga2_2009_Jan_08_1109.bof
bGOUT_1SFA_DC3_fpga2_2009_Jan_08_1338.bof
bGOUT_1SFA_DC3_fpga2_2009_Jan_09_1251.bof
bGOUT_1SFA_DC_fpga2_2009_Jan_07_1555.bof
bGOUT_1SFA_fpga2_2008_Dec_15_1347.bof

Notes:
  • The "1SFA" FPGA2 designs allow faster readout times by dropping some channels on output (only 4064 channels are sent out).
  • These are meant to work with 4096-channel FPGA1/3 designs - which ones should be used?
  • Output packet format is slightly different: 8-byte frame count, 8128 bytes data (4064 channels), 8 byte error flag, 16 bytes unused space.
  • New registers:
    • ROL_SEL=0 for 2-pol (I, Q) output, ROL_SEL=1 for full-Stokes.
    • BW_SEL=0 for 100, 200 or 400 MHz BW, BW_SEL=1 for 800 MHz.
Topic revision: r3 - 2010-02-15, PaulDemorest
 

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